Input buffer circuits are commonly used in Input/Output (I/O) units of Integrated Circuit (IC) devices for receiving data input signals from external systems. When the received data input signals have a voltage level that is greater than the supply voltage of the integrated circuit device, the input buffer transitions the received data input signals to the supply voltage level of the integrated circuit device. With the ever increasing speed requirements of conventional integrated circuit devices, there has been a corresponding need for high-speed input buffers. In order to increase the speed of input buffer circuits and to lower power consumption IC manufacturers have moved to thin gate oxide fabrication processes. However, the high voltage of the input signal can cause breakdown of the gate oxide. In addition, these input buffer circuits can suffer from duty cycle distortion.
In order to solve these problems, one prior art input buffer uses a NMOS transistor in series with the input terminal to limit the voltage swing at the gate oxide of an input inverter, thus protecting the thin gate oxide of the NMOS pull-down transistor and the PMOS pull-up transistor. To reduce the supply current when the input is high, a pull-up circuit (e.g. PMOS transistor gated by the output) is used to pull up the input of the inverter when the input signal is substantially more than the trigger voltage of the inverter. However, the problem of duty cycle distortion exists in this type of input buffer circuit because the voltage at the node of the pull-up circuit and the input of the inverter is time dependent. In other words, the voltage at the input of the prior art inverter depends on its previous value when the input signal changed states. Furthermore, this type of prior art input buffer circuit may have unwanted DC current flow in to the input terminal when the input signal is transitioning from high to low
Thus, there is a need for a high speed input buffer circuit that can tolerate high voltage input signals. Moreover, there is a need for an input buffer that has low power consumption and that does not have duty cycle distortion. The present invention meets the above needs.